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high speed converter evaluation platform hsc-adc-evalc rev. 0 evaluation boards are only intended for device evaluation and not for production purposes. evaluation boards as supplied as is and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. no license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. analog devices reserves the right to change devices or specifications at any time without notice. trademarks and registered trademarks are the property of their respective owners. evaluation boards are not authorized to be used in life support devices or systems. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features xilinx virtex-4 fpga-based buffer memory board used for capturing digital data from high speed adc evaluation boards to simplify evaluation 64 kb fifo depth parallel input at 644 msps sdr and 800 msps ddr supports 1.8 v, 2.5 v, and 3.3 v cmos and lvds interfaces supports multiple adc channels up to 18 bits measures performance with visualanalog real-time fft and time domain analysis analyzes snr, sinad, sfdr, and harmonics simple usb port interface (2.0) supports adcs with serial port interfaces (spi) fpga reconfigurable via jtag, on-board eprom, or usb on-board regulator circuit speeds setup 5 v, 3 a switching power supply included compatible with windows 98 (2nd edition), windows 2000, windows me, and windows xp equipment needed analog signal source and antialiasing filter low jitter clock source high speed adc evaluation board and adc data sheet pc running windows 98 (2nd edition), windows 2000, windows me, or windows xp latest version of visualanalog usb 2.0 port recommended (usb 1.1 compatible) product highlights 1. easy to set up. connect the included power supply along with the clk and ain signal sources to the two evaluation boards. then connect to the pc via the usb port and evaluate the performance instantly. 2. usb port connection to pc. pc interface is via a usb 2.0 connection (1.1 compatible) to the pc. a usb cable is provided in the kit. 3. 64 kb fifo. the on-board fpga contains an integrated fifo to store data captured from the adc for subsequent processing. 4. up to 644 msps sdr/800 msps ddr encode rates on each channel. multichannel adcs with encode rates up to 644 msps sdr and 800 msps ddr can be used with the adc capture board. 5. supports adcs with serial port interface or spi. some adcs include a feature set that can be changed via the spi. the adc capture board supports these spi-driven features through the existing usb connection to the computer without additional cabling needed. 6. visualanalog?. visualanalog supports the hsc-adc- evalc hardware platform as well as enabling virtual adc evaluation using adisimadc?, analog devices proprietary behavioral modeling technology. this allows rapid compari- son between multiple adcs, with or without hardware evaluation boards. for more information, see an-737 at www.analog.com/visualanalog . functional block diagram 06676-001 fpga configuration mode ext sync2 led2 led1 fifo control(9) j1* j2* j3* j10 reconfig data(16) ext sync1 *data converter i/o connectors data bus 1(18) clkb(2) fpga gpio(8) spi(7) usb direct(5) data bus 2(18) clka(2) fpga done fpga config prom usb config prom jtag connector power connector usb connector usb controller capture upload portc portb portd porte porta onboard voltage regulators j4 clock input filtered analog input logic spi adc n n j6 usb standard usb 2.0 on-board voltage regulators power connector fpga single or multichannel high speed adc evaluation board hsc-adc-evalc clock circuit figure 1.
hsc-adc-evalc rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 equipment needed........................................................................... 1 product highlights ........................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 product description......................................................................... 3 evaluation board description......................................................... 3 evaluation board hardware ............................................................ 4 hsc-adc-evalc adc capture board easy start ............... 4 power supplies .............................................................................. 4 connection and setup ................................................................. 4 jumpers .......................................................................................... 5 hsc-adc-evalc adc capture board features.................. 6 hsc-adc-evalc supported adc evaluation boards........ 7 theory of operation .........................................................................8 configuration ................................................................................8 input circuitry...............................................................................8 data capture ..................................................................................8 code description ..........................................................................8 fpga configuration and customization..................................8 evaluation board schematics and artwork...................................9 hsc-adc-evalc schematics...................................................9 pcb layout ................................................................................. 23 i/o connectorj1, j2, and j3 pin mapping .......................... 24 ordering information.................................................................... 28 bill of materials (rohs compliant) ........................................ 28 ordering guide .......................................................................... 30 esd caution................................................................................ 30 revision history 4/07revision 0: initial version
hsc-adc-evalc rev. 0 | page 3 of 32 product description the analog devices, inc. high speed converter evaluation platform (hsc-adc-evalc) includes the latest version of visualanalog and an fpga-based buffer memory board to capture blocks of digital data from the analog devices high speed analog-to-digital converter (adc) evaluation boards. the adc capture board is connected to the pc through a usb port and is used with visualanalog to quickly evaluate the performance of high speed adcs. users can view an fft for a specific analog input and encode rate to analyze snr, sinad, sfdr, and harmonic information . the adc capture board is easy to set up. additional equipment needed includes an analog devices high speed adc evaluation board, a signal source, and a clock source. once the kit is connected and powered, the evaluation is enabled instantly on the pc. the adc capture board enables numerous expansion and evaluation possibilities by virtue of its powerful reconfigurable fpga core. the system can acquire digital data at speeds up to 644 msps single data rate (sdr) and 800 msps double data rate (ddr). the fpga contains an integrated fifo memory that allows capture of data record lengths up to a total of 64 kb. a usb 2.0 microcontroller communicating with visualanalog allows for easy interfacing to newer computers using the usb 2.0 (usb 1.1 compatible) interface. evaluation board description the adc capture board provides all of the support circuitry required to accept two 18-bit channels from an adcs parallel cmos or lvds outputs. various functions such as fpga configuration load options and i/o logic levels can be selected by proper connection of various jumpers or switches (see table 1 ). when using the hsc-adc-evalc in conjunction with an adc evaluation board, it is critical that the signal sources used for the adc boards analog input and clock have very low phase noise (<1 ps rms jitter) to achieve the ultimate performance of the converter. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. see figure 5 to figure 20 for complete schematics and layout plots.
hsc-adc-evalc rev. 0 | page 4 of 32 evaluation board hardware hsc-adc-evalc adc capture board easy start requirements ? hsc-adc-evalc adc capture board, visualanalog, 5 v wall transformer, and usb cable ? high speed adc evaluation board and adc data sheet ? power supply for adc evaluation board ? analog signal source and appropriate filtering ? low jitter clock source applicable for specific adc evaluation, typically <1 ps rms jitter ? pc running windows? 98 (2nd edition), windows 2000, windows me, or windows xp ? pc with a usb 2.0 port recommended (usb 1.1 compatible) easy start steps mprtant te ministratie rigts fr te ins perating systems are neee uring te entire easy start preure mpletin f eery step efre reerting t a nrmal user me is remmene install visualanalog from the cd provided in the adc capture board kit or download the latest version from the web. for the latest updates to the software, check the analog devices website at www.analog.com/fifo . 2. connect the adc capture board to the adc evaluation board. if an adapter is required, insert the adapter between the adc evaluation board and the adc capture board. 3. connect the provided usb cable to the adc capture board and to an available usb port on the computer. 4. refer to table 1 for setting the adc capture board?s i/o logic level to match the level coming from the adc evalua- tion board. 1.8 v is default; 2.5 v and 3.3 v are jumper selectable. most evaluation boards can be used with the default settings. 5. the adc capture board is supplied with a wall mount switching power supply. connect the supply end to an ac wall outlet rated for 100 vac to 240 vac at 47 hz to 63 hz. the other end is a 2.1 mm inner diameter jack that connects to the pcb at j4. 6. once the usb cable is connected to both the computer and the hsc-adc-evalc board, and power is applied, the usb driver starts to install. the found new hardware wizard opens and prompts you through the automated install process. 7. (optional) verify in the windows device manager that analog devices adc-hsc-evalc is listed under the usb hardware. 8. refer to the instructions included in the respective adc data sheet found at www.analog.com/fifo for more information about connecting the adc evaluation board?s power supply and other requirements. after verification of power supply connections, apply power to the adc evaluation board and check the voltage levels on the adc board to make sure they are correct. 9. make sure the evaluation boards are powered on before connecting the analog input and clock. connect the appropriate analog input (which should be filtered with a band-pass filter) and low jitter clock signal. 10. refer to the visualanalog user manual at analogcoi for detailed softare operating instructions power supplies the adc capture board is supplied with a wall mount switch- ing power supply that provides a 5 v, 3 a maximum output. connect the supply to the rated 100 vac to 240 vac wall outlet at 47 hz to 63 hz. the other end is a 2.1 mm inner diameter jack that connects to the pcb at j4. on the pc board, the supply is fused and conditioned before connecting to the regulators that supply the proper bias to the entire adc capture board. connection and setup the adc capture board has two 40-pin connectors (j2 and j3) that accept two 18-bit channels of parallel cmos or lvds inputs from the adc (see figure 2 ). the third 40-pin connector (j1) is used to pass spi and other usb/fpga control signals across to adjacent adc evaluation boards that support these features.
hsc-adc-evalc rev. 0 | page 5 of 32 rohde & schwarz, smhu, 2v p-p signal synthesizer rohde & schwarz, smhu, 2v p-p signal synthesizer band-pass filter usb connection 06676-004 hsc-adc-evalc data capture board pc running visualanalog ?+ ps gnd v reg 5v dc 3a max wall outle t 100v to 240v ac 47hz to 63hz data bus 2 parallel lvds/cmos outputs evaluation board data bus 1 parallel lvds/cmos outputs xfmr input clk switching power supply spi spi onboard power supply figure 2. example setup using adc evaluation board and hsc-adc-evalc adc capture board jumpers default settings ale lists te efault settings fr te sde ealuatin it ale umper nfiguratins jumper number description j9, pin 1 to pin 2 (1.8 v) default. sets fpga i/o voltage to 1.8 v logic (hardwired, do not remove). j9, pin 3 to pin 4 (2.5 v) install single jumper here to set fpga i/o voltage to 2.5 v logic. j9, pin 5 to pin 6 (3.3 v) install single jumper here to set fpga i/o voltage to 3.3 v logic. table 2. fpga configuration mode u4 dip switch setting m0 m1 m2 m3 m4 fpga configured via eeprom on on on reserved reserved fpga configured via usb (default) on off off reserved reserved
hsc-adc-evalc rev. 0 | page 6 of 32 hsc-adc-evalc adc capture board features 06676-002 general purpose i/o, usb/spi control data bus 1 data bus 2 fpga load select on board power supply 100mhz oscillator fpga i/o voltage mode fpga config prom xilinx virtex-4 fpga debug pins external sync i/o cypress usb controller usb connector fpga jtag connector 5vdc power input figure 3. hsc-adc-evalc components (top view)
hsc-adc-evalc rev. 0 | page 7 of 32 06676-003 figure 4. hsc-adc-evalc components (bottom view) hsc-adc-evalc supported adc evaluation boards refer to the analog devices adc capture board product page at www.analog.com/fifo for a list of hsc-adc-evalc-compatible adc evaluation boards. some legacy adc boards may require interposer cards to facilitate proper pin mapping to the adc capture boar d. if needed, the interposer part number is noted in the compatibility table at www.analog.com/fifo for the respective data converter.
hsc-adc-evalc rev. 0 | page 8 of 32 theory of operation the hsc-adc-evalc evaluation platform is based around the virtex-4 fpga (xc4vfx20-10ffg672c) from xilinx?, which can be programmed through visualanalog to operate with a variety of data converters. another key component, the cypress usb device (u3), communicates with a host pc and provides the spi interface used for configuration. configuration some converter devices require programming for mode or feature selection, which the spi controller accomplishes using spi-accessible register maps. u3 drives the 4-wire spi (sclk, sdi, sdo, csb 1 ) signals to the converter board via connector (j1). for more information on serial port interface (spi) func- tions, consult the user manual titled interfacing to high speed adcs via spi at www.analog.com/fifo . the spi interface designed on the cypress ic can communicate with up to five different spi-enabled devices including the fpga. the clk and sdi/sdo data lines are common to all spi devices. the desired spi-enabled device is selected for control by using one of the five active low chip select (cs) pins. this functionality is controlled by selecting a spi channel in the spi controller software. at power-up, visualanalog attempts to autodetect the converter that is attached to the adc capture board using the spi interface. if a recognized device is found, visualanalog selects the appropriate fpga configuration; otherwise, the user is prompted to make the device selection. in either case, visualanalog then programs the fpga using the spi interface of u3. the configurations typically program a fifo data capture function within the fpga. input circuitry the parallel data input pins of the fpga, which interface to the converter, are configurable. they can operate with 1.8 v, 2.5 v, or 3.3 v logic levels and can accept lvds or cmos inputs. each channel of the adc capture board requires a clock signal to capture data. these clock signals are normally provided by the attached adc evaluation board and are passed along with the data through one or more pins on connector j2 and/or connector j3. refer to the hsc-adc-evalc i/o connector pin mappings shown in figure 21 and figure 22 . data capture the process of filling the fifo and reading the data back requires several steps. 1. visualanalog initiates the fifo fill process by resetting the fifos. 2. the 48 mhz usb read clock (rclk) is then suspended to ensure that it does not add noise to the adc input. 3. visualanalog waits approximately 30 ms to allow for data capture before beginning the readback process. this wait time is an adjustable parameter in visualanalog. 4. visualanalog reads the data from the fifo through the usb interface to the pc. code description fpga configuration files are provided by adi for all adcs supported by the hsc-adc-evalc evaluation platform. these files are designed and tested to facilitate quick performance evaluations of analog devices data converters. no additional fpga programming is required from the user for typical operation. fpga configuration and customization users can manually customize or update the fpga code through a jtag connector (j10) provided on the adc capture board, as shown in figure 17 . however, analog devices provides no support or guarantee of performance if the provided code is customized by the user. the hsc-adc-evalc hardware platform may contain addi- tional circuit functions to support future developments and capabilities. these functions are not supported beyond the scope of this data sheet and the analog devices supplied data- capture fpga routines at this time. additional fpga programming support may be available through the users local xilinx representative or distributor. 1 note that csb1 is the default csb line used.
hsc-adc-evalc rev. 0 | page 9 of 32 evaluation board schematics and artwork hsc-adc-evalc schematics 0 6676-005 tyco and dsp ez?kit connector to fpga xc4vfx20-10ffg672c xc4vfx20-10ffg672c xc4vfx20-10ffg672c xc4vfx20-10ffg672c r38 100? r39 100? r50 51.1 ? figure 5.
hsc-adc-evalc rev. 0 | page 10 of 32 0 6676-006 sram address and control fpga controls u21 nc7sz05m5x r1 100 ? r40 3.74k ? r44 3.74k ? r42 3.74k ? r41 3.74k ? r43 3.74k ? xc4vfx20-10ffg672c r28 3.74k ? r27 249? r33 249? r25 3.74k ? r31 3.74k ? figure 6.
hsc-adc-evalc rev. 0 | page 11 of 32 fpga to sram dat a xc4vfx20-10ffg672c 06676-007 xc4vfx20-10ffg672c figure 7.
hsc-adc-evalc rev. 0 | page 12 of 32 a d19 t o be used with higher density sram devices 06676-008 figure 8.
hsc-adc-evalc rev. 0 | page 13 of 32 sram and fpga powe r 06676-009 xc4vfx20-10ffg672c xc4vfx20-10ffg672c r66 499 ? r64 499 ? r65 499 ? r63 499? figure 9.
hsc-adc-evalc rev. 0 | page 14 of 32 06676-010 refclk oscillator for idelayctrl fpga bypass cap sram a bypass cap sram b bypass cap + + + + r15 24? figure 10.
hsc-adc-evalc rev. 0 | page 15 of 32 06676-011 debug pins unused rocket i/0 connections xc4vfx20-10ffg672c xc4vfx20-10ffg672c figure 11.
hsc-adc-evalc rev. 0 | page 16 of 32 06676-012 rocket i/0 connections figure 12.
hsc-adc-evalc rev. 0 | page 17 of 32 06676-013 usb connections r49 3.74 ? r71 3.74 ? r48 100k ? sdi & sdo directions are with respect to the device under control. usb direct i/o (3.3v) figure 13.
hsc-adc-evalc rev. 0 | page 18 of 32 usb connections (continued) 06676-014 4 5 2 1 3 6 r52 3.74k ? r72 3.74k ? r46 499? xc4vfx20-10ffg672c xc4vfx20-10ffg672c j6 figure 14.
hsc-adc-evalc rev. 0 | page 19 of 32 06676-015 ez?kit expansion interface ? for dsps p1 p2 p3 figure 15.
hsc-adc-evalc rev. 0 | page 20 of 32 , 06676-016 tyco hm ? zd connectors j1 hs-serial/spi/aux j2 data bus 1 j3 data bus 2 figure 16.
hsc-adc-evalc rev. 0 | page 21 of 32 0 6676-017 configuration eepro m jtag connector eeprom hardware reconfiguration pushbutton r57 3.74k ? r73 zero r77 100? r78 100? r75 3.74k ? r76 3.74k ? figure 17.
hsc-adc-evalc rev. 0 | page 22 of 32 power and voltage regulators 06676-018 + + + + + + + + + tsw?102?08?g?d do not remove r68 147k figure 18.
hsc-adc-evalc rev. 0 | page 23 of 32 pcb layout 06676-019 general purpose i/o, usb/spi control data bus 1 data bus 2 xilinx virtex-4 fpga debug pins external sync i/o cypress usb controller usb connector fpga jtag connector 5vdc power input fpga load select on board power supply 100mhz oscillator fpga i/o voltage mode fpga config prom figure 19. top silkscreen 06676-020 figure 20. bottom silkscreen
hsc-adc-evalc rev. 0 | page 24 of 32 i/o connectorj1, j2, and j3 pin mapping d c b a d c b a d c b a d17a? d16a? d14a? d12a? d10a ? d8a? d6a? d4a? d2a? d0a? d17a+ d16a+ d14a+ d12a+ d10a + d8a+ d6a+ d4a+ d2a+ d0a+ dclka1? d15a? d13a? d11a? d9a? d7a? d5a? d3a? d1a? dclka2? dclka1+ d15a+ d13a+ d11a+ d9a+ d7a+ d5a+ d3a+ d1a+ dclka2+ lvds data path > cmos/lvds data path > lvds data path > cmos/lvds data path > d17b? d16b? d14b? d12b? d10b? d8b? d6b? d4b? d2b? d0b? d17b+ d16b+ d14b+ d12b+ d10b+ d8b+ d6b+ d4b+ d2b+ d0b+ dclkb1? d15b? d13b? d11b? d9b? d7b? d5b? d3b? d1b? dclkb2? dclkb1+ d15b+ d13b+ d11b+ d9b+ d7b+ d5b+ d3b+ d1b+ dclkb2+ (j2) data bus 1 (j3) data bus 2 06676-021 figure 21. j2 and j3 pin mapping
hsc-adc-evalc rev. 0 | page 25 of 32 d c b a d c b a mgtclk1? sd1? sd2? sd3? sd4? sd5? sd6? sd7? sd8? mgtclk2? mgtclk1+ sd1+ sd2+ sd3+ sd4+ sd5+ sd6+ sd7+ sd8+ mgtclk2+ i/o_1 i/o_3 i/o_5 i/o_7 sclk sdi sdo usb_1 usb_2 usb_4 i/o_2 i/o_4 i/o_6 i/o_8 csb_1 csb_2 csb_3 csb_4 usb_3 usb_5 (j1) hs-serial/spi/aux high speed serial reference clk high speed serial data inputs future high speed serial data inputs fpga general purpose i/o spi control (3.3v) usb direct i/o (3.3v) 06676-022 figure 22. j1 pin mapping hs-serial/spi/aux j1 j2 data bus 1 j3 data bus 2 1.4m m 13.843mm 38mm 32mm 43.155mm 06676-023 figure 23. data converter i/o connector placement (top view)
hsc-adc-evalc rev. 0 | page 26 of 32 table 3. hsc-adc-evalc j1 i/o connections to fpga (u1) connector j1 (hs-serial, spi, aux) schematic net name fpga pin a1 usb_5 none b1 usb_4 none c1 mgtclk2+ af10 d1 mgtclk2? af11 a2 usb_3 none b2 usb_2 none c2 none none d2 none none a3 csb_4 none b3 usb_1 none c3 none none d3 none none a4 csb_3 none b4 sdo h12 c4 none none d4 none none a5 csb_2 none b5 sdi k12 c5 none none d5 none none a6 csb_1 none b6 sclk h13 c6 sd4+ af7 d6 sd4? af8 a7 i/o_8 ad3 b7 i/o_7 ac3 c7 sd3+ ac1 d7 sd3? ad1 a8 i/o_6 aa3 b8 i/o_5 y3 c8 sd2+ g1 d8 sd2? h1 a9 i/o_4 w3 b9 i/o_3 v3 c9 sd1+ a4 d9 sd1? a3 a10 i/o_2 p3 b10 i/o_1 n3 c10 mgtclk1+ k1 d10 mgtclk1? l1 table 4. hsc-adc-evalc j2 i/o connections to fpga (u1) connector j2 (data bus 1) schematic net name fpga pin a1 dclkb2+ c13 b1 dclkb2? c12 c1 d0b+ t4 d1 d0b? t3 a2 d1b+ m4 b2 d1b? n4 c2 d2b+ p4 d2 d2b? r3 a3 d3b+ m5 b3 d3b? l5 c3 d4b+ l4 d3 d4b? l3 a4 d5b+ k3 b4 d5b? j3 c4 d6b+ l7 d4 d6b? m6 a5 d7b+ j4 b5 d7b? h3 c5 d8b+ k6 d5 d8b? j5 a6 d9b+ g5 b6 d9b? f4 c6 d10b+ h4 d6 d10b? g4 a7 d11b+ h8 b7 d11b? h7 c7 d12b+ g7 d7 d12b? h6 a8 d13b+ f8 b8 d13b? f7 c8 d14b+ k8 d8 d14b? k7 a9 d15b+ b9 b9 d15b? a9 c9 d16b+ a8 d9 d16b? a7 a10 dclkb1+ a12 b10 dclkb1? b12 c10 d17b+ b10 d10 d17b? a10
hsc-adc-evalc rev. 0 | page 27 of 32 table 5. hsc-adc-evalc j3 i/o connections to fpga (u1) connector j3 (data bus 2) schematic net name fpga pin a1 dclka2+ c14 b1 dclka2? b14 c1 d0a+ d6 d1 d0a? e6 a2 d1a+ h9 b2 d1a? g9 c2 d2a+ e8 d2 d2a? e7 a3 d3a+ l10 b3 d3a? l9 c3 d4a+ j9 d3 d4a? k10 a4 d5a+ c3 b4 d5a? d3 c4 d6a+ e3 d4 d6a? f3 a5 d7a+ d5 b5 d7a? e5 c5 d8a+ c4 d5 d8a? d4 a6 d9a+ b7 b6 d9a? c7 c6 d10a+ b6 d6 d10a? c6 a7 d11a+ d9 b7 d11a? c9 c7 d12a+ d8 d7 d12a? c8 a8 d13a+ c11 b8 d13a? b11 c8 d14a+ e10 d8 d14a? d10 a9 d15a+ g10 b9 d15a? f10 c9 d16a+ e11 d9 d16a? d11 a10 dclka1+ a14 b10 dclka1? a13 c10 d17a+ g12 d10 d17a? g11
hsc-adc-evalc rev. 0 | page 28 of 32 ordering information bill of materials (rohs compliant) table 6. qty reference designator description manufacturer part number 1 pcb pcb, adc evaluation platform moog/pcsm gs09156x8 0 bga1, bga2 ic, 18-bit ddrii sram 2-word burst operation (mos integrated circuit), do not install nec pd44164362f5-eq1 2 c1, c2 capacitor, 470 pf, 50 v ceramic x7r 0402 panasonic/ecg ecj-0eb1h471k 3 c10, c17, c33 capacitor, 330 f, 10 v tg smd panasonic/ecg eeetg1a331p 2 c21, c22 capacitor, 68 pf, 50 v, ceramic 0402 smd panasonic/ecg ecu-e1h680jcq 67 c3, c25 to c30, c34, c37 to c45, c59, c60, c63 to c72, c74 to c76, c78 to c85, c88 to c92, c96 to c98, c100 to c106, c113 to c118, c120 to c125 capacitor, 0.1 f, 10 v, ceramic x5r 0402 panasonic/ecg ecj-0eb1a104k 1 c32 capacitor, 10 f, 6.3 v, tantalum te series kemet t491a106m006at 2 c35, c36 capacitor, 12 pf, 50 v, ceramic 0402 smd panasonic/ecg ecj-0ec1h120j 18 c4, c6, c7, c9, c11 to c14, c16, c18, c20, c62, c77, c87, c93, c95, c99, c119 capacitor, 0402 chip, x5r, 6.3 v, 1 f, 20% panasonic ecj-0eb0j105m 7 c46, c48, c52, c61, c73, c86, c126 capacitor, 10 f, 20 v, tantalum tel smd avx tpsc106k025r0500 2 c47, c51 capacitor, 47 f, 10 v, tantalum tel smd epcos, inc. b45197a2476k309 2 c49, c50 capacitor, 1000 pf, 50 v, ceramic y5v 0402 panasonic/ecg ecj-0ef1h102z 17 c5, c19, c23, c24, c31, c53 to c58, c107 to c112 capacitor, 0402 chip, x5r, 6.3 v, 0.22 f, 10% panasonic ecj-0eb0j224k 1 c94 capacitor, 470 pf, 25 v, ceramic 0402 smd panasonic/ecg ecj-0eb1e471k 7 d1, d2, d6 to d10 led green, clear lens smd panasonic lnj308g8tra 1 d3 polyswitch surface-mount (ptc devices) international irf rectifiers 30bq015trpbf 2 d4, d5 40 v silicon high current schottky barrier diode zetex semiconductors zhcs2000 1 j1, j2, j3 connector, 2-pair 10 column high speed hm-zd pcb mount tyco 6469028-1 1 j10 connector, 2 mm, 2 7 pin smt vertical male, with shroud molex 87832-1420-tb32 1 j4 connector, dc power jack cui inc. pj-102ah 1 j6 connector, usb type b mill-max 897-43-004-90-000000 2 j5,j7 connector, end launch jack/pcb, 62 mil, gold emerson 142-0701-801 1 j8 connector, 25 mil square postheader, 100 mil, 2 7 samtec, inc. tsw-107-08-g-d 1 j9 (2.5 v and 3.3 v) connector, 2 2 header, 100 mil samtec, inc. tsw-102-08-g-d 1 j9 (jumper pin 1 to jumper pin 2) solder wire jumper (pin 1 indicator to 1.8 v on silkscreen) 1 l1 inductor, 4.6 h smd, code 0004 sumida cdr7d28mn4r6 1 l2 inductor, 3.6 h smd, code 0003 sumida cdr7d28mn3r6
hsc-adc-evalc rev. 0 | page 29 of 32 qty reference designator description manufacturer part number 17 l3 to l19 ferrite chip, 220 , 2 a, 0603, 100 mhz tdk mpz1608s221a 3 p1 to p3 connector, 0.050 in 0.050 in, samtec tfm series, 2r samtec, inc. tfm-145-32-s-d-a 13 r1, r3, r4, r34 to r39, r61, r67, r77, r78 resistor, 100 , 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf1000x 3 r15, r56, r74 resistor, 24 , 1/16 w, 5%, 0402 smd panasonic/ecg erj-2gej240x 1 r16 resistor, 75 k, 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf7502x 5 r17, r18, r23, r24, r50 resistor, 51.1 , 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf51r1x 10 r19 to r22, r46, r62 to r66 resistor, 499 , 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf4990x 1 r2 resistor, 40.2 k, 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf4022x 17 r25, r28, r31, r40 to r45, r49, r52, r57, r58, r71, r72, r75, r76 resistor, 3.74 k, 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf3741x 1 r26 resistor, 169 k, 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf1693x 2 r27, r33 resistor, 249 , 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf2490x 1 r68 resistor, 147 k, 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf1473x 1 r29 resistor, 226 k, 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf2263x 0 r30 resistor, 140 k, 1/16 w, 1%, 0402 smd, do not install panasonic/ecg erj-2rkf1403x 1 (r32), r79 resistor, 107 k, 1/16 w, 1%, 0402 smd, do not install r32 panasonic/ecg erj-2rkf1073x 1 r47 resistor, 76.8 k, 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf7682x 2 r48, r59 resistor, 100 k, 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf1003x 3 r5, r6, r73 resistor 0 , 1/16 w, 5%, 0402 smd panasonic/ecg erj-2ge0r00x 2 r53, r70 resistor 80.6 k, 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf8062x 1 r54 resistor, low value, 1206 smd, 0.04 tt electronics lrc-lr1206lf-01-r040-f 1 r55 resistor, low value, 1206 smd, 0.06 tt electronics lrc-lr1206lf-01-r060-f 2 r60, r69 resistor, 25.5k , 1/16 w, 1%, 0402 smd panasonic/ecg erj-2rkf2552x 2 r7, r8 resistor array network, 8 to 22 chip panasonic exb-2hv220jv 1 s1 fuse, polyswitch smt (ptc devices) tyco smd250f-2 1 t1 choke, common-mode coils, wire- wound type for large current dlw5ah/dlw5bs series (2014/2020 size) murata dlw5bsn191sq2 1 u1 virtex-4 fpga xilinx xc4vfx20-10ffg672c 2 u10, u20 voltage regulator, high accuracy, low iq, adjustable analog devices adp3334acpz-reel7 2 u11, u15 voltage regulator, high accuracy ultralow iq, 1.5 a analog devices adp3339akcz-2.5r7 1 u12 crystal oscillator, 24 mhz, 12 pf, smd ecs ecs-240-12-4x 1 u13 1.8 v, 8 mb, platform flash-in system xilinx xcf08pfsg48c 1 u16 voltage regulator, 1.5 a ultralow dropout linear regulator national semiconductor lp38842s-1.2 1 u18 crystal controlled oscillator (100 mhz fixed frequency oscillator) connor-winfield corp. cwx823-100.0m 0 u19 156.25 mhz low jitter saw crystal oscillator, do not install epson electronics america eg-2121ca 156.2500m-phpal3 2 u2, u17 ic, constant frequency current-mode, step-down, dc-to-dc controller in tsot analog devices adp1864aujz-r7 1 u21 ic, single inverter buffer/driver with open-drain output fairchild semiconductor nc7sz05m5x 1 u3 ic, ez-usb fx2lp usb microcontroller cypress semiconductor corp. cy7c68013a-128axc 1 u4 switch, 5-position, smt, dip cts 219-5mst 1 u5 ic, 128-bit i 2 c bus serial eeprom microchip 24lc00-i/sn
hsc-adc-evalc rev. 0 | page 30 of 32 qty reference designator description manufacturer part number 2 u6, u7 ic, p-channel enhancement mode field effect transistor fairchild semiconductor ndt456p 1 u8 voltage regulator, high accuracy ultralow iq, 1.5 a analog devices adp3339akcz-3.3 1 u9 switch, 6 mm light touch sw, n.o. alps skhhaka010 4 h1, h2, h3, h4 circuit board support on base richco, inc. cbsb-14-01 1 packed with pcb transformer 5 v, 3 a switcher p5 cui, inc. dps050300u-p5p-tk 0 u14 1.2 v precision low noise shunt voltage references, sot-23 (rt-3), do not install analog devices adr512art 0 r9 resistor, 6.2 k, 1/16 w, 5%, 0402 smd, do not install panasonic/ecg erj-2gej622x 0 r12, r13, r14, r51 resistor, 0 , 1/16 w, 5%, 0402 smd, do not install panasonic/ecg erj-2ge0r00x 0 r11 resistor 13 k , 1/16 w, 5%, 0402 smd, do not install panasonic/ecg erj-2gej133x 0 r10 resistor 1.0 k, 1/16 w, 5%, 0402 smd, do not install panasonic/ecg erj-2gej102x 0 c8 capacitor, 0402 smd, x5r, 6.3 v, 0.22 f, 10%, do not install panasonic ecj-0eb0j224k 0 c15 0402 chip capacitor, x5r, 6.3 v, 1 f, 20%, do not install panasonic ecj-0eb0j105m ordering guide model description hsc-adc-evalc data converter evaluation platform HSC-ADC-EVALCZ 1 data converter evaluation platform 1 z = rohs compliant part. esd caution
hsc-adc-evalc rev. 0 | page 31 of 32 notes
hsc-adc-evalc rev. 0 | page 32 of 32 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. eb06676-0-4/07(0)

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